The present invention relates to a read only memory (hereinafter, referred to as xe2x80x9cROMxe2x80x9d), and more particularly to a read error preventive technology in a large scale ROM.
Referring to FIG. 2, there is shown a schematic constitutional diagram of a conventional ROM.
The conventional ROM has column lines CLi (i=1 to m) and word lines WLj (j=1 to n) arranged intersecting the column lines. At intersections between the column lines CLi and the word lines WLj, memory cells 1i,j formed by N-channel insulated gate transistors (hereinafter, an insulated gate transistor is referred to as xe2x80x9cMOSxe2x80x9d and an N-channel MOS is as xe2x80x9cNMOSxe2x80x9d) are selectively arranged and drains of the memory cells 1i,j are connected to the column lines CLi and gates of the memory cells are connected to the word lines WLj. Sources of the memory cells 1i,j are connected to ground potential GND via a conductive line.
Respective column lines CLi are connected in common to a bit line BL via P-channel MOS (hereinafter, referred to as xe2x80x9cPMOSxe2x80x9d) transistors 2i. Selection signals SLi are given to gates of the respective PMOS transistors 2i for selecting one of the PMOS transistors 2i so as to be set on. Furthermore, respective column lines CLi are connected to a power supply potential VCC via PMOS transistors 3i controlled in common by a pre-charge signal PR. The bit line BL is connected to the power supply potential VCC via a PMOS transistor 4 which is constantly on.
The ROM has a reference column line CLr arranged intersecting word lines WLj. At each intersection between the reference column line CLr and each word line WLj, each reference memory cell 5j formed by an NMOS transistor is arranged and a drain of the reference memory cell 5j is connected to the reference column line CLr and its gate is connected to the word line WLj. A source of each reference memory cell 5j is connected to ground potential GND. The column line CLr is connected to a reference bit line BLr via a PMOS transistor 6 controlled by a selection signal SLr and connected to the power supply potential VCC via a PMOS transistor 7 controlled by the pre-charge signal PR. The reference bit line BLr is connected to the power supply VCC via a PMOS transistor 8 which is constantly on.
The bit line BL and the reference bit line BLr are connected to a sense amplifier 9. The sense amplifier 9 amplifies an electric potential difference between the bit line BL and the reference bit line BLr and outputs a status of a selected memory cell 1i,j as an output signal Q.
In the conventional ROM, each memory cell 1i,j is set to a logical value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d at manufacturing. For example, in a contact ROM, a conductive line between a source of a memory cell 1i,j and the ground potential GND is connected in a contact layer and the memory cell is set to xe2x80x9c1,xe2x80x9d while the sources are disconnected from the ground potential GND without a formation of the contact layer and the memory cell is set to xe2x80x9c0.xe2x80x9d Therefore, if the selected memory cell 1i,j is set to xe2x80x9c1,xe2x80x9d the memory cell 1i,j is set on, by which current flows. If it is set to xe2x80x9c0,xe2x80x9d the current does not flow. On the other hand, all of the reference memory cells 5j are set to xe2x80x981.xe2x80x9d
Next, an operation is described below.
In the conventional ROM, for example, it is assumed that a memory cell 11,1 is set to xe2x80x9c0xe2x80x9d and memory cells 11,2 to 11,n are set to xe2x80x9c1,xe2x80x9d respectively.
If a level xe2x80x9cLxe2x80x9d is given to selection signals SL1 and SLr to select the column line CL1 and the reference column line CLr and the word line WL1 is selected to give a level xe2x80x9cH,xe2x80x9d the memory cell 11,1 is read out to the bit line BL and the reference memory cell 51 is to the reference bit line BLr, respectively. As the memory cell 11,1 is set to xe2x80x9c0,xe2x80x9d no current flows through the memory cell 11,1. In addition, memory cells 11,2 to 11,n connected in parallel between the column line CL1 and the ground potential GND are set off since they are not selected, and therefore the electric potential of the bit line BL is substantially equal to the power supply potential VCC.
On the other hand, all of the reference memory cells 51 to 5n are set to xe2x80x9c1xe2x80x9d and therefore the reference memory cell 51 selected by the word line WL1 is set on and other non-selected reference memory cells 52 to 5n are set off. Therefore, an electric potential of the reference bit line BLr is substantially equal to an electric potential obtained by dividing the power supply potential VCC by xe2x80x9conxe2x80x9d resistance of the PMOS transistors 8 and 6 and of the reference memory cell 51. An electric potential difference between the bit line BL and the reference bit line BLr is amplified by the sense amplifier 9. In the case the electric potential of the bit line BL is higher than that of the reference bit line BLr, and therefore a content of the selected memory cell 11,1 is judged to be xe2x80x9c0xe2x80x9d and an output signal Q of xe2x80x9cLxe2x80x9d is output from the sense amplifier 9.
Next, if a word line WL2 is selected and xe2x80x9cHxe2x80x9d is given, the memory cell 11,2 is read out to the bit line BL and the reference memory cell 52 is to the reference bit line BLr, respectively. The memory cell 11,2 is set to xe2x80x9c1xe2x80x9d and therefore the memory cell 11,2 is set on. Other memory cells 11,3 to 11,n connected in parallel between the column line CL1 and the ground potential GND, which are not selected, are set off. Accordingly, the electric potential of the bit line BL is substantially equal to an electric potential obtained by dividing the power supply potential VCC by xe2x80x9conxe2x80x9d resistance of the PMOS transistors 4 and 21 and of the memory cell 11,2.
On the other hand, the electric potential of the reference bit line BLr is substantially equal to an electric potential obtained by dividing the power supply potential VCC by xe2x80x9conxe2x80x9d resistance of the PMOS transistors 8 and 6 and of the reference memory cell 52. In the case the electric potential of the bit line BL is substantially equal to that of the reference bit line BLr, and therefore a content of the selected memory cell 11,1 is judged to be xe2x80x9c1xe2x80x9d by the sense amplifier 9 and an output signal Q of xe2x80x9cHxe2x80x9d is output.
There is, however, a problem as described below in the conventional ROM.
Memory cells 1i,1 to 1i,n are connected in parallel between the column line CLi and the ground potential GND. At an read operation, only a single memory cell 1i,j selected according to a word line WLj is set on and other memory cells are set off. Since each memory cell 1i,j is formed by an NMOS transistor, xe2x80x9coffxe2x80x9d resistance in an off condition is extremely high compared with xe2x80x9conxe2x80x9d resistance in an on condition, though it is impossible to generate a completely non-conducting state to remove leak current in an off condition (which is referred to as xe2x80x9coff leak currentxe2x80x9d).
Accordingly, there has been such a problem that if there are a great number of (for example, 1024) memory cells 1i,1 to 1i,n connected in parallel, off leak current flowing through these memory cells totals up to a value equivalent to current flowing through the memory cell in an on condition, by which it becomes hard to judge an electric potential difference by using the sense amplifier 9. Particularly in a mass storage ROM having a micro-structure, ratios of the xe2x80x9coffxe2x80x9d resistance and the xe2x80x9conxe2x80x9d resistance are decreased by an application of a low voltage, which also causes a problem that an appropriate ROM cannot be designed.
According to the invention, there is provided a ROM capable of resolving these problems of the prior art as described above by eliminating effects of off leak current of non-selected memory cells to prevent a read error even if it is a large scale ROM.
It is an object of the present invention to prevent a read error by decreasing effects of leak current. To achieve the object, a read only memory having a typical constitution of the present invention comprises word lines activated in response to an address signal, sense lines intersected with the word lines and selected in response to a selection signal, a reference sense line intersected with the word lines, memory cells storing data therein, reference memory cells connected to the reference sense line, a sense amplifier for comparing currents flowing on the selected one of the sense lines and on the reference sense line, and a correction current supply circuit connected to the sense lines and the reference sense line, the correction current supply circuit generating a correction current approximately corresponding to a leak current flowing through the memory cells connected to the selected one of the sense lines and providing the correction current to the sense lines and the reference sense line.